This invention relates to a programmable logic cell and particularly to a programmable logic cell for use in a programmable gate array.
Programmable gate arrays comprise a large number of logic cells linked together by a routing network.
In general each logic cell has n inputs and k outputs, the k outputs being provided as inputs to a k to 1 multiplexor. However it is often advantageous to have a single output from the logic cell, so the logic cell may incorporate a multiplexor to provide a single output. Further multiplexors are provided to allow the logic cells to be linked up as required to allow their individual logic functions to be built up into a complex program by linking the output of each logic cell to the input of another in an appropriate manner.
A problem in programmable gate arrays is that they generally require data to travel through a very large number of logic cells in series and as a result the delay between data being supplied to the array and coming from the array can be unacceptably long.
In order to overcome this problem it is desirable to minimise the time delay imposed by each individual logic cell.
This invention is intended to provide a logic cell having the smallest possible delay in order to overcome this problem.